In semiconductor design, separate voltage supplies can be connected to NMOS and PMOS bulk regions in triple-well CMOS technologies. Modification of these voltages with respect to the primary power and ground supplies is called well-biasing. In some applications, these voltages may be modulated to provide a back-bias voltage (“back biasing”), aiming to increase or decrease threshold voltage (Vth) in order to adjust the trade-off relation between performance and power dissipation of the device.
Generally speaking, back-biasing techniques range from the fairly basic (e.g., with a common bias for the whole chip) to the very sophisticated (e.g., a separate bias for each block). The available techniques also depend on technology-specific characteristics. For example, Silicon-over-Insulator (SOI) technologies provide a number of different transistor device options. One such option is called LVT or flipped-well transistors which consists of a PMOS transistor having P-type well (bulk) underneath its insulator layer and a NMOS transistor having N-type well (bulk) underneath its insulator layer. The forward-back-biasing (FBB) technique applied to logic gate regions, commonly referred to as Sea-of-Gates (SoG), built with flipped-well transistors (LVT), is based on biasing the P and N wells underneath the PMOS and NMOS devices, respectively, with symmetrically matched negative and positive voltage levels that are normally selectable or programmable.
The inventors hereof have recognized that various applications require that transitions between different biasing levels be achieved with no stop to logic switching. In those applications, P and N well voltages must be symmetrically biased at all times (including during well bias level transitions) in order to avoid timing violations. Moreover, it is highly desirable for level transitions to be as fast as possible in order to optimize product performance.